Job Title: FPGA Design Engineer
Job Type: Contract
Duration: 6-Months (Convert to permanent after)
Location: Cambridge or Bristol
Candidates are required to do hybrid working in one of Cambridge or Bristol.
Our client make hardware-accelerated architecture enables real-time transactional AI at scale, eliminating bottlenecks in data-intensive environments.
Main Responsibilities:
Design, develop, and verify FPGA modules in Verilog/SystemVerilog and VHDL
Translate novel functional computing models into optimised RTL architectures
Implement high-throughput, pipelined digital logic and memory interfaces
Contribute to simulation, synthesis, debug, and validation of designs on Altera Agilex FPGAs and/or AMD Xilinx Versal
Collaborate on architectural evaluation of latency, power, and scalability
Write clean, maintainable RTL and contribute to documentation, DFT/DFM, and version control workflows
Key Requirements:
Minimum 7 years of post-graduate experience in digital hardware design (FPGA/ASIC) and Verilog/SystemVerilog experience (or 15 years total experience with strong VHDL background)
High-level logic synthesis and simulation tools
Hands-on experience with Intel Quartus Prime Pro toolchain
RTL design in Verilog/SystemVerilog and/or VHDL
Tech Stack:
Quartus Prime Pro, Vivado, ModelSim, Questa
Verilog, SystemVerilog
C, C++, Python, Haskell, Erlang, TCL
Git, Jira
Desirables:
PCI3 Gen 6 experience
Experience with Intel/Altera Agilex 5E FPGAs
VHDL
Exposure to compute-in-memory, functional or dataflow architectures
UVM or equivalent verification experience
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